`include "defines.d"
// This is the source file
module source (clock, v_o, r_i, d_o, reset);
	parameter id_bit = 0;
	parameter mem_depth = 32;
	parameter addr_sz = 6;
	parameter mem_width = 34;
	input clock, reset;
	output wire v_o;
	input r_i;
	output wire [mem_width-1:0] d_o;
	reg [addr_sz-1:0] addr;
	
	reg [mem_width-1:0] mem [mem_depth-1:0];
	reg [mem_depth:0] counter;	
	reg finishedTransmission;
	assign v_o = ~finishedTransmission;
	always @ (posedge clock or negedge reset) begin
		if (~reset) begin// synthesis loop_limit 256
			for(counter = 0; counter < mem_depth; counter=counter+1) begin
				if(counter % 3 == 0) begin // heads
					mem[counter] <= {`HEAD,3'b000, 3'b000, id_bit, counter[24:0]};
				end
				else if(counter %3 == 1) begin // bodies
					mem[counter] <= {`BODY, id_bit, counter[30:0]};
				end
				else if(counter %3 == 2) begin // tails
					mem[counter] <= {`TAIL, id_bit, counter[30:0]};
				end
			end
			addr <= 0;
			finishedTransmission <= 0;
		end
		else begin
			addr <= (r_i & v_o & (addr < 31)) ? addr + 1 : addr;

			if ( (~finishedTransmission) & (addr == 31) & (r_i) )
				finishedTransmission <= 1;
			else if (~finishedTransmission) 
				finishedTransmission <= 0;
			else
				finishedTransmission <= 1;
		end

	end	assign d_o = mem[addr];
	

endmodule 
